Conventionally, a memory device receives a power supply voltage VEXT and a ground voltage VSS from outside and generates an internal voltage of various types required for operating various parts of the internal circuit.
Various types of internal voltages include a core voltage, a peripheral voltage, and a high power voltage. A core voltage is supplied to a core region of the memory device, that is, a memory cell array. A peripheral voltage is supplied to a peripheral circuit of the core region, that is, the circuit arranged outside the memory cell array and for connection with the memory cell array. A high voltage is used for driving a word line and the others similar.
FIG. 1 shows an example of the conventional internal voltage generator used in a memory device.
In FIG. 1, a bandgap reference circuit 100 (well known by those skilled in the pertinent art) receives an external voltage VEXT and outputs a bandgap reference voltage Vbg.
A first reference voltage generating circuit 101 receives the bandgap reference voltage Vbg and outputs a first reference voltage Vref1 having a voltage level. A second reference voltage generating circuit 102 receives the bandgap reference voltage Vbg and outputs a second reference voltage Vref2 also having a voltage level.
A core voltage generating unit 103 receives the first reference voltage Vref1 and outputs a core voltage Vcore for use in the core region of the memory device.
An internal voltage generator for peripheral region 104 receives the second reference voltage Vref2 and outputs a peripheral voltage Vperi for use in the peripheral circuit.
A high voltage generating unit 106 equipped with a high voltage pumping unit detects the voltage level of a high voltage Vpp applied to the word line and then outputs a stable high voltage.
An internal voltage control unit 105 receives a plurality of signals pwr_up, rpcg, ratv, and cke to output a control signal act_i. As shown in FIG. 1, the control signal act_i controls the operations of the core voltage generating unit 103, the internal voltage generator for peripheral region 104, and the high voltage generating unit 106.
FIG. 2 is a circuit diagram of the internal voltage control unit 105 shown in FIG. 1.
The signals pwrup, rpcg, ratv as shown in FIGS. 1-2 are defined as follows:
(1) The signal pwrup is a power up signal indicating that the external voltage VEXT is applied;
(2) The signal rpcg is a signal enabled if the memory device enters into a precharge mode;
(3) The signal ratv is a signal enabled if the memory device enters into an active mode; and
(4) The signal cke is a clock enable signal used in a synchronous memory device.
Referring to FIGS. 1-2, the signal pwrup is in a low level until the external voltage VEXT reaches a stable level. The power up signal pwrup then is in a high level after the external voltage VEXT reaches the stable level.
The signal ratv generates a low pulse when the memory device enters into the active mode. FIG. 3 shows the low pulse signal ratv.
The signal rpcg generates the low pulse to exit the active mode and enter into the precharge mode. FIG. 3 shows the low pulse signal rpcg.
The signal cke remains high level while the memory device is operating and transits to the low level when the memory device enters into a power down mode.
FIG. 3 is a signal pulse diagram of the circuit shown in FIG. 2.
As shown in FIG. 3, the control signal act_i remains high level during two low pulse signals ratv and rpcg. If the low pulse signal ratv is generated by an active command, the signal act_i transits to a high level. The high level signal act_i will then transit to a low level when the signal rpcg of low pulse is generated.
The operations of a conventional memory device having a conventional internal voltage generator are described below referring to FIGS. 1-3.
The bandgap reference circuit 100 receives the external voltage VEXT supplied to the memory device and outputs the bandgap reference voltage Vbg having a predetermined voltage level. Typically, the voltage level of the external voltage VEXT supplied from outside is unstable. The bandgap reference circuit 100 receives such unstable external voltage VEXT and outputs the bandgap reference voltage Vbg that maintains a stable voltage level.
The first reference voltage generating circuit 101 and the second reference voltage generating circuit 102 adjust the bandgap reference voltage Vbg and generate the voltages Vref1 and Vref2, respectively, as a basis for generating the internal voltages Vcore and Vperi, respectively, that are necessary for internal operations of the memory device.
The core voltage generating unit 103 generates the core voltage Vcore used in the core region using the first reference voltage Vref1 when it is enabled by the control signal act_i.
The internal voltage generator for peripheral region 104 generates the peripheral voltage Vperi used in the peripheral circuit using the second reference voltage Vref2 when it is enabled by the control signal act_i.
The high voltage generating unit 106 is also enabled by the control signal act_i and detects the level of the high voltage Vpp and then outputs a high voltage of a certain predetermined level (which could be Vpp) by utilizing the pumping operation. The high voltage Vpp is a voltage used for word line driving, or other similar driving operations in a memory device.
The internal voltage control unit 105 generates the control signal act_i that enables the core voltage generating unit 103, the internal voltage generator for peripheral region 104, and the high voltage generating unit 106.
As shown in FIGS. 2-3, the memory device enters into an active mode when the active signal ratv is applied as a low level pulse, and the memory device enters into a precharge mode when the precharge signal rpcg is inputted as a low level pulse.
Now referring to FIG. 3, the memory device enters into an active section (signaled by the low level pulse ratv) from a precharge section, and, during the active section, the memory device enters into a read/write operation section for performing the corresponding read/write operations if a read/write command is applied, and then enters back into the precharge section if the active section terminates (when signaled by the low level pulse rpcg).
Thus, all of the core voltage generating unit 103, the internal voltage generator for peripheral region 104, and the high voltage generating unit 106 are operated during the entire active section (including the read/write operation section).
However, there could be certain sections in the active section (see FIG. 3 bottom, for example, when act_i is high level) that do not require operating the core voltage generating unit 103, or the internal voltage generator for peripheral region 104, or the high voltage generating unit 106. For example, the time between the beginning of the active section and the input of a read/write command, the core voltage generating unit 103 and the others like such as 104 and 106 may be disabled (possibly after a prescribed time delay after entering into the active mode) without causing operational problems.
However, in the conventional memory devices, the core voltage generating unit 103, the internal voltage generator for peripheral region 104, and the high voltage generating unit 106 are operated continuously during the active mode, which causes unnecessary power consumption.